A Power and Performance Simulator for a Single-Chip Message-Passing Parallel Architecture

Single-chip parallel computer architectures may provide a solution to the wire latency problem expected as device fecture sizes shrink. Hence the development of efficient single-chip parallel computer is an active area of research. Extensive design space exploration of such architectures requires an architectural simulator that evaluates both power and performance. The available parallel computer simulators model only shared memory systems and do not support power modeling. This paper presents a powerperformance simulator, ScmpSim, for a single-chip messagepassing parallel architecture. ScmpSim is a cycle-by-cycle simulation environment that models the processor nodes and the message-passing network with excellent flexibility for design variations. It provides an infrastructure that researchers can easily extend to model new message-passing multi-computer architectures1.